| Signal Name | Direction | Description |
|---|---|---|
| m_axib_araddr [AXI_ADR_WIDTH-1:0] |
O | This signal is the address for a memory mapped read to the user logic from the host. |
|
m_axib_arid [ID_WIDTH-1:0] |
O | Master read address ID. |
| m_axib_arlen[7:0] | O | Master read address length. |
| m_axib_arsize[2:0] | O | Master read address size. |
| m_axib_arprot[2:0] | O | 3’h0 |
| m_axib_arvalid | O | The assertion of this signal means there is a valid read request to the address on m_axib_araddr. |
| m_axib_arready | I | Master read address ready. |
| m_axib_arlock | O | 1’b0 |
| m_axib_arcache[3:0] | O | 4’h0 |
| m_axib_arburst | O | Master read address burst type. |