| Attribute | Description |
|---|---|
| RV | Reserved |
| RW | Read/Write |
| RC | Clear on Read. |
| W1C | Write 1 to Clear |
| W1S | Write 1 to Set |
| RO | Read Only |
| WO | Write Only |
Some registers can be accessed with different attributes. In such cases different register offsets are provided for each attribute. Undefined bits and address space is reserved. In some registers, individual bits in a vector might represent a specific DMA engine. In such cases the LSBs of the vectors correspond to the H2C channel (if any). Channel ID 0 is in the LSB position. Bits representing the C2H channels are packed just above them.