The Completion Status is located at the last location of Completion ring, that is, Completion Ring Base Address + (Size of the completion length (8,16,32) * (Completion Ring Size – 1)).
In order to make the QDMA write Completion Status
to the Completion ring, Completion Status must be enabled in the Completion context.
In addition to affecting Interrupts, the trigger mode defined in the Completion
context also moderates the writing of Completion Statuses. Subject to
Interrupt/Status moderation, a Completion Status can be written when either of the
following happens:
- A CMPT packet is written to the Completion ring.
- A CMPT-CIDX update from the SW is received, and indicates that more Completion entries are waiting to be read.
- The timer associated with the respective CMPT QID expires and is programmed in a timer-based trigger mode.
| Bit | Bit Width | Field Name | Description |
|---|---|---|---|
| [63:37] | 27 | Reserved | |
| [36:35] | 2 | error |
Error. 0x0: No error 0x1 Bad CIDX update received 0x2: Descriptor error 0x3: CMPT ring overflow error |
| [34:33] | 2 | int_state | Interrupt State. 0: ISR 1: TRIG |
| [32] | 1 | color | Color status bit |
| [31:16] | 16 | cidx | Consumer Index (RO) |
| [15:0] | 16 | pidx | Producer Index |