PCIe to AXI BARs - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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1.0 English

For each physical function, the PCIe configuration space consists of a set of six 32-bit memory BARs and one 32-bit Expansion ROM BAR. When SR-IOV is enabled, an additional six 32-bit BARs are enabled for each Virtual Function. These BARs provide address translation to the AXI4 memory mapped space capability, interface routing, and AXI4 request attribute configuration. Any pairs of BARs can be configured as a single 64-bit BAR. Each BAR can be configured to route its requests to the QDMA register space, the Bridge AXI4-Lite master interface, or the AXI MM bridge master interface.

Request Memory Type

The memory type can be set for each PCIe BAR through attributes attr_dma_pciebar2axibar_*_cache_pf*.

  • AxCache[0] is set to 1 for modifiable, and 0 for non-modifiable.
  • AxCache[1] is set to 1 for cacheable, and 0 for non-cacheable.