AXI Bridge Subsystem Limitations - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
Release Date
1.0 English
  1. For this subsystem, the bridge master and bridge slave cannot achieve more than 128 Gb/s.

  2. Bridge will be compliant with all MPS and MRRS settings; however, all traffic initiated from the Bridge will be limited to 256 Bytes (max).
  3. AXI address width is limited to 48 bits.