Features - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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1.0 English
  • The PCIe Integrated Block is supported in VersalĀ® ACAP.
  • Supports 64, 128, 256, and 512-bit data path.
  • Supports x1, x2, x4, x8, or x16 link widths.
  • Supports Gen1, Gen2, and Gen3 link speeds. Gen4 for PCIE4C block.
  • Support for both the AXI4 Memory Mapped and AXI4-Stream interfaces per queue.
  • 2048 queue sets
    • 2048 H2C descriptor rings.
    • 2048 C2H descriptor rings.
    • 2048 C2H Completion (CMPT) rings.
  • Supports Polling Mode (Status Descriptor Write Back) and Interrupt Mode.
  • Interrupts
    • 2048 MSI-X vectors.
    • Up to 8 MSI-X per function.
      Note: It is possible to assign more vectors per function. For more information, see AR 72352.
    • Interrupt aggregation.
  • C2H Stream interrupt moderation.
  • C2H Stream Completion queue entry coalescence.
  • Descriptor and DMA customization through user logic
    • Allows custom descriptor format.
    • Traffic Management.
  • Supports SR-IOV with up to 4 Physical Functions (PF) and 252 Virtual Functions (VF)
    • Thin hypervisor model.
    • QID virtualization.
    • Allows only privileged/Physical functions to program contexts and registers.
    • Function level reset (FLR) support.
    • Mailbox.
  • Rich programmability on a per queue basis, such as AXI4 Memory Mapped versus AXI4-Stream interfaces.