The Configuration Extend interface allows the core to transfer configuration information with the user application when externally implemented configuration registers are implemented.
Port Name | I/O | Width | Description |
---|---|---|---|
cfg_ext_read_received | O | 1 | Configuration Extend Read Received The core asserts this output when it has
received a configuration read request from the link. Set when
PCI Express Extended
Configuration Space Enable is selected
in the user defined configuration Capabilities tab in in the
Vivado®
IDE.
|
cfg_ext_write_received | O | 1 | Configuration Extend Write Received The core asserts
this output when it has received a configuration write request
from the link. Set when PCI Express Extended
Configuration Space Enable is selected
in Capabilities tab in the Vivado IDE.
|
cfg_ext_register_number | O | 10 | Configuration Extend Register Number The 10-bit address of the configuration register being read or written. The data is valid when cfg_ext_read_received or cfg_ext_write_received is High. |
cfg_ext_function_number | O | 8 | Configuration Extend Function Number. The 8-bit function number corresponding to the configuration read or write request. The data is valid when cfg_ext_read_received or cfg_ext_write_received is High. |
cfg_ext_write_data | O | 32 | Configuration Extend Write Data Data being written into a configuration register. This output is valid when cfg_ext_write_received is High. |
cfg_ext_write_byte_enable | O | 4 | Configuration Extend Write Byte Enable Byte enables for a configuration write transaction. |
cfg_ext_read_data | I | 32 | Configuration Extend Read Data You can provide data from an externally implemented configuration register to the core through this bus. The core samples this data on the next positive edge of the clock after it sets cfg_ext_read_received High, if you have set cfg_ext_read_data_valid. |
cfg_ext_read_data_valid | I | 1 | Configuration Extend Read Data Valid The user application asserts this input to the core to supply data from an externally implemented configuration register. The core samples this input data on the next positive edge of the clock after it sets cfg_ext_read_received High. The core expects the assertions of this signal within 262144 ('h4_0000) clock cycles of user clock after receiving the read request on cfg_ext_read_received signal. If no response is received by this time, the core will send auto-response with 'h0 payload, and the user application must discard the response and terminate that particular request immediately |