The completion context is used by the Completion Engine.
| Bit | Bit Width | Field Name | Description |
|---|---|---|---|
| [256:183] | 17 | Reserved. Initialize to 0. | |
| [182:180] | 3 | port_id |
Port ID. The Completion Engine checks the port_id of events received at its input to the port_id configured here. If the check fails, the input is dropped, and an error is logged in the C2H_ERR_STAT register. The following are checked for port_id: 1. All events on the s_axis_c2h_cmpt interface. These include CMPTs, Immediate data, markers and VirtIO control messages. 2. CMPT CIDX pointer updates (checked only when the update is coming from the AXI side). |
| [179] | 1 | Reserved. Initialize to 0's | |
| [178:175] | 4 | baddr4_low |
Since the minimum alignment supported is 64B in this case, this field must be 0 |
| [174:147] | 28 | Reserved. Initialize to 0's | |
| [146] | 1 | dir_c2h |
DMA direction is C2H. The CMPT engine can be used to manage the completion/used ring of a C2H as well as an H2C queue. 0x0: DMA direction is H2C 0x1: DMA direction is C2H |
| [145] | 1 | Reserved. Initialize to 0 | |
| [144] | 1 | dis_int_on_vf | Disable interrupt with VF |
| [143] | 1 | int_aggr | Interrupt Aggregration Set to configure the QID in interrupt aggregation mode |
| [142:132] | 11 | vec | Interrupt Vector Number |
| 131 | 1 | at |
Address Translation This bit is used to determine whether the queue addresses are translated or untranslated. This information is sent to the PCIe on CMPT and Status writes. 0: Address is untranslated 1: Address is translated |
| 130 | 1 | ovf_chk_dis |
Completion Ring Overflow Check Disable If set, then the CMPT Engine does not check whether writing a completion entry in the Completion Ring will overflow the Ring or not. The result is that QDMA invariably sends out Completions without first checking if it is going to overflow the Completion Ring and not take any actions that it normally takes when it encounters a Completion Ring overflow scenario. It is up to the software and user logic to negotiate and ensure that they do not cause a Completion Ring overflow |
| [129] | 1 | full_upd | Full Update If reset, the all fields other than the CIDX of a Completion-CIDX-update are ignored. Only the CIDX field will be copied from the update to the context. If set, the Completion CIDX update can update the following fields in this context:
|
| [128] | 1 | timer_running | If set, it indicates that a timer is running on this queue. This timer is for the purpose of CMPT interrupt moderation. Ideally, the software must ensure that there is no running timer on this QID before shutting the queue down. This is a field used internally by the hardware. The software must initialize it to 0 and then treat it as read-only. |
| [127] | 1 | user_trig_pend | If set, it indicates that a user logic initiated interrupt is pending to be generated. The user logic can request an interrupt through the s_axis_c2h_cmpt_ctrl_user_trig signal. This bit is set when the user logic requests an interrupt while another one is already pending on this QID. When the next Completion CIDX update is received by QDMA, this pending bit may or may not generate an interrupt depending on whether or not there are entries in the Completion ring waiting to be read. This is a field used internally by the hardware. The software must initialize it to 0 and then treat it as read-only. |
| [126:125] | 2 | err | Indicates that the Completion Context is in
error. This is a field written by the hardware. The software must
initialize it to 0 and then treat it as read-only. The following
errors are indicated here: 0: No error. 1: A bad CIDX update from software was detected. 2: A descriptor error was detected. 3: A Completion packet was sent by the user logic when the Completion Ring was already full. |
| [124] | 1 | valid | Context is valid. |
| [123:108] | 16 | cidx | Current value of the hardware copy of the Completion Ring Consumer Index. |
| [107:92] | 16 | pidx | Completion Ring Producer Index. This is a field written by the hardware. The software must initialize it to 0 and then treat it as read-only. |
| [91:90] | 2 | desc_size | Completion Entry Size: 0: 8B 1: 16B 2: 32B 3: 64B |
| [89:32] | 58 | baddr | 64B aligned base address of Completion ring – bit [63:6]. |
| [31:28] | 4 | qsize_idx | Completion ring size index. This index selects one of 16 register (offset 0x204 :0x240) which has different ring sizes. |
| [27] | 1 | color | Color bit to be used on Completion. |
| [26:25] | 2 | int_st | Interrupt State: 0: ISR 1: TRIG This is a field used internally by the hardware. The software must initialize it to 0 and then treat it as read-only. When out of reset, the hardware initializes into ISR state, and is not sensitive to trigger events. If the software needs interrupts or status writes, it must send an initial Completion CIDX update. This makes the hardware move into TRIG state and as a result it becomes sensitive to any trigger conditions. |
| [24:21] | 4 | timer_idx | Index to timer register for TIMER based trigger modes. |
| [20:17] | 4 | counter_idx | Index to counter register for COUNT based trigger modes. |
| [16:13] | 4 | Reserved. Initialize to 0 | |
| [12:5] | 8 | fnc_id | Function ID |
| [4:2] | 3 | trig_mode |
Interrupt and Completion Status Write Trigger Mode: 0x0: Disabled 0x1: Every 0x2: reserved 0x3: User 0x4: User_Timer 0x5: reserved |
| [1] | 1 | en_int | Enable Completion interrupts. |
| [0] | 1 | en_stat_desc | Enable Completion Status writes. |