AXI4-Stream C2H Write Completion Ports - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. AXI-ST C2H Write Completion Port Descriptions
Port Name I/O Description
axis_c2h_dmawr_cmp O This signal is asserted when the last data payload write request of the packet gets the write completion. It is one pulse per packet.