IRQ Block User Interrupt Enable Mask (0x04) - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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Table 1. IRQ Block User Interrupt Enable Mask (0x04)
Bit Index Default Access Type Description
[NUM_USR_INT-1:0] 'h0 RW


User Interrupt Enable Mask

0: Prevents an interrupt from being generated when the user interrupt source is asserted.

1: Generates an interrupt on the rising edge of the user interrupt source. If the Enable Mask is set and the source is already set, a user interrupt will be generated also.