The slave bridge provides termination of memory-mapped AXI4 transactions from an AXI4 master device (such as a processor). The slave bridge provides a
way to translate addresses that are mapped within the AXI4 memory mapped address domain to the domain addresses for PCIe.
Write transactions to the Slave Bridge are converted into one or more MemWr TLPs, depending on the configured Max Payload
Size setting, which are passed to the integrated block for PCI Express. When a
remote AXI master initiates a read transaction to the slave bridge, the read address
and qualifiers are captured and a MemRd request
TLP is passed to the core and a completion timeout timer is started. Completions
received through the core are correlated with pending read requests and read data is
returned to the AXI4 master. The slave bridge
can support up to 32 AXI4 write requests, and
32 AXI4 read requests.
Note: If slave reads and writes are
valid, IP prioritizes reads over writes. You are recommended to have proper
arbitration (leave some gaps between reads so writes can pass through).