AXI4 Memory Mapped Write Interface Signals - 1.0 English

AXI4 Memory Mapped Write Interface Signals - 1.0 English - PG344

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2022-05-20

Version

1.0 English

Table 1. AXI4 Memory Mapped Write Interface Signals
Signal Name	Direction	Description
m_axi_wdata [DATA_WIDTH-1:0]	O	Master write data.
m_axi_wlast	O	Master write last.
m_axi_wstrb	O	Master write strobe.
m_axi_wvalid	O	Master write valid.
m_axi_wready	I	Master write ready.
m_axi_wuser [DATA_WIDTH/8-1:0]	O	Parity ports for read interface. This port is enabled only in Propagate Parity mode.