Config Write Flush Timeout (0x60) - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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Table 1. Config Write Flush Timeout (0x60)
Bit Index Default Access Type Description
4:0 5’h0 RW

Write Flush Timeout

Applies to AXI4-Stream C2H channels. This register specifies the number of clock cycles a channel waits for data before flushing the write data it already received from PCIe. This action closes the descriptor and generates a writeback. A value of 0 disables the timeout. The timeout value in clocks = 2value.