PCIe to DMA Address Format - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. PCIe to DMA Address Format
31:16 15:12 11:8 7:0
Reserved Target Channel Byte Offset
Table 2. PCIe to DMA Address Field Descriptions
Bit Index Field Description
15:12 Target The destination submodule within the DMA

4’h0: H2C Channels

4’h1: C2H Channels

4’h2: IRQ Block

4’h3: Config

4’h4: H2C SGDMA

4’h5: C2H SGDMA

4’h6: SGDMA Common

4'h8: MSI-X
11:8 Channel ID[3:0] This field is only applicable for H2C Channel, C2H Channel, H2C SGDMA, and C2H SGDMA Targets. This field indicates which engine is being addressed for these Targets. For all other Targets this field must be 0.
7:0 Byte Offset The byte address of the register to be accessed within the target. Bits[1:0] must be 0.