Status writebacks and/or interrupts are generated automatically by hardware
based on the queue context. When wbi_intvl_en is set,
writebacks/interrupts will be sent based on the interval selected in the register
QDMA_GLBL_DSC_CFG (0x250) bits[2:0]. Due to the slow nature of interrupts, in interval
mode, interrupts may be late or skip intervals. If the wbi_chk context bit is set, a writeback/interrupt will be sent when the
descriptor engine has detected that the last descriptor at the current PIDX has
completed. It is recommended the wbi_chk bit be set for
all internal mode operation, including when interval mode is enabled. An interrupt will
not be generated until the irq_arm bit has been set by
software. Once an interrupt has been sent the irq_arm
bit is cleared by hardware. Should an interrupt be needed when the irq_arm bit is not set, the interrupt will be held in a
pending state until the irq_arm bit is set.
Descriptor completion is defined to be when the descriptor data transfer has completed and its write data has been acknowledged on AXI (H2C bresp for AXI MM, Valid/Ready of ST), or been accepted by the PCIe Controller’s transaction layer for transmission (C2H MM).