IRQ Block User Interrupt Request (0x40) - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. IRQ Block User Interrupt Request (0x40)
Bit Index Default Access Type Description
[NUM_USR_INT-1:0] ‘h0 RO

user_int_req

User Interrupt Request

This register reflects the interrupt source AND’d with the enable mask register.