Speed Change Related Issue
- Description
- Repeated speed changes can result in the link not coming up to the intended targeted speed.
- Workaround
- A follow-on attempt should bring the link back. In extremely rare scenarios, a full reboot might be required.
Link Autonomous Bandwidth Status (LABS) Bit
- Description
- As a Root Complex when performing the link width/rate
changes, the link width change works as expected. However, the PCIe protocol
requires a LABS bit which is not getting set after the link width/rate
change.Note: This is an informational bit and does not impact actual functionality.
- Workaround
- Ensure the software / application ignores the LABS bit as
this is an informational bit and does not impact functionality.Note: For any application, Xilinx recommends that you make sure the link is quiesced and no transactions are pending before performing any link rate changes.
AXI Bridge
-
For this subsystem, the bridge master and bridge slave cannot achieve more than 128 Gb/s.
- Bridge will be compliant with all MPS and MRRS settings; however, all traffic initiated from the Bridge will be limited to 256 Bytes (max)
- AXI address width is limited to 48 bits.
PCIe Transaction Type
The PCIe® transactions generated are those that are compatible with the AXI4 specification. The following table lists the supported PCIe transaction types.
| TX | RX |
|---|---|
| MRd32 | MRd32 |
| MRd64 | MRd64 |
| MWr32 | MWr32 |
| MWr64 | MWr64 |
| Msg | Msg |
| Cpl | Cpl |
| CplD | CplD |
| Cfg Type0/1 (For Root Port) |
AXI Slave
- Only supports the INCR burst type. Other types result in the Slave Illegal Burst (SIB) interrupt.
- No memory type support (
AxCACHE) - No protection type support (
AxPROT) - No lock type support (
AxLOCK) - No non-contiguous byte enable support (
WSTRB)
AXI Master
- Only issues the INCR burst type
- Only issues the data, non-secure, and unprivileged protection type