Descriptor Bypass Mode Writeback/Interrupts - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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In bypass mode, the user logic has explicit control over status updates to the host, and marker responses back to user logic. Along with each descriptor submitted to the Descriptor Bypass Input Port for a Memory Mapped Engine (H2C and C2H) or H2C Stream DMA engine, there is a CIDX, and sdi field. The CIDX is used to identify which descriptor has completed in any status update (host writeback, marker response, or coalesced interrupt) generated at the completion of the descriptor. If the sdi field of the descriptor was input, then a writeback to the host will be generated if the context wbk_en bit is set. An interrupt can also be sent if the sdi bit is set if the context irq_en and irq_arm bits are set.

If interrupts are enabled, the user logic must monitor the traffic manager output for the irq_arm. After the irq_arm bit has been observed for the queue, a descriptor with the sdi bit will be sent to the DMA. Once a descriptor with the sdi bit has been sent, another irq_arm assertion must be observed before another descriptor with the sdi bit can be sent. If the user sets the sdi bit when the arm bit has not be properly observed, an interrupt may or may not be sent, and software might hang indefinitely waiting for an interrupt. When interrupts are not enabled, setting the sdi bit has no restriction. However excessive writeback events can severely reduce the descriptor engine performance and consume write bandwidth to the host.

Descriptor completion is defined to be when the descriptor data transfer has completed and its write data has been acknowledged on AXI4 (H2C bresp for AXI MM, Valid/Ready of ST), or been accepted by the PCIe Controller’s transaction layer for transmission (C2H MM).