H2C Channel Performance Cycle Count (0xC4)

H2C Channel Performance Cycle Count (0xC4) - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2022-05-20

Version

1.0 English

Table 1. H2C Channel Performance Cycle Count (0xC4)
Bit Index	Default	Access Type	Description
31:0	32’h0	RO	pmon_cyc_count[31:0] Increments once per clock while running. See the Performance Monitor Control register (0xC0) bits Clear and Auto for clearing.