If MSI is enabled, this register specifies the MSI vector number of the MSI. In legacy interrupts, only the 2 LSB of each field should be used to map to INTA, B, C, or D.
Similar to the other C2H/H2C bit packing clarification, see the previous figure. The first C2H vector is after the last H2C vector. For example, if NUM_H2C_Channel = 1, then H2C0 vector is at 0xA0, bits [4:0], and C2H Channel 0 vector is at 0xA0, bits [12:8]. If NUM_H2C_Channel = 4, then H2C3 vector is at 0xA0 28:24, and C2H Channel 0 vector is at 0xA4, bits [4:0].
| Bit Index | Default | Access Type | Description |
|---|---|---|---|
| 28:24 | 5’h0 | RW |
vector3 The vector number that is used when an interrupt is generated by channel 3. |
| 20:16 | 5’h0 | RW |
vector2 The vector number that is used when an interrupt is generated by channel 2. |
| 12:8 | 5’h0 | RW |
vector1 The vector number that is used when an interrupt is generated by channel 1. |
| 4:0 | 5’h0 | RW |
vector0 The vector number that is used when an interrupt is generated by channel 0. |