IP Facts - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
Release Date
1.0 English
LogiCORE™ IP Facts Table
Subsystem Specifics
Supported Device Family 1 Versal® ACAP and Versal Premium ACAP
Supported User Interfaces AXI4 Memory Map, AXI4-Lite, AXI4-Stream
Resources QDMA and AXI Bridge Subsystems: Performance and Resource Utilization

XDMA Subsystem: Performance and Resource Utilization

Provided with Subsystem
Design Files Encrypted System Verilog
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Constraints File (XDC)
Simulation Model Verilog
Supported S/W Driver 2 QDMA Subsystem and AXI Bridge Subsystem: Linux, DPDK, and Windows Drivers

XDMA Subsystem: Linux, and Windows Drivers

Tested Design Flows 3
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Release Notes and Known Issues Master Answer Record: AR 75397
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. See the "Application Software Development" chapter in the QDMA Subsystem, and XDMA Subsystem sections below.
  3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.