IRQ Block User Vector Number (0x8C) - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2022-05-20
Version
1.0 English

If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In legacy interrupts only the 2 LSB of each field should be used to map to INTA, B, C, or D.

Table 1. IRQ Block User Vector Number (0x8C)
Bit Index Default

Access Type

 Description
28:24 5’h0 RW

vector 15

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[15].
20:16 5’h0 RW

vector 14

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[14].
12:8 5’h0 RW

vector 13

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[13].
4:0 5’h0 RW

vector 12

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[12].