The target bridge receives requests from the host. Based on BARs, the requests are directed to the internal target user through the AXI4-Lite master, or the CQ bypass port. After the downstream user logic has returned data for a non-posted request, the target bridge generates a read completion TLP and sends it to the PCIe IP over the CC bus.
In the following tables, the PCIe BARs selection corresponds to the options set in the PCIe BARs tab in the IP Configuration GUI.
| PCIe BARs Selection During IP Customization | BAR0 (32-bit) | BAR1 (32-bit) | BAR2 (32-bit) |
|---|---|---|---|
| Default | DMA | ||
| PCIe to AXI Lite Master enabled |
PCIe to AXI4-Lite Master |
DMA | |
| PCIe to AXI Lite Master and PCIe to DMA Bypass enabled | PCIe to AXI4-Lite Master | DMA | PCIe to DMA Bypass |
| PCIe to DMA Bypass enabled | DMA | PCIe to DMA Bypass |
| PCIe BARs Selection During IP Customization | BAR0 (64-bit) | BAR2 (64-bit) | BAR4 (64-bit) |
|---|---|---|---|
| Default | DMA | ||
| PCIe to AXI Lite Master enabled | PCIe to AXI4-Lite Master | DMA | |
| PCIe to AXI Lite Master and PCIe to DMA Bypass enabled | PCIe to AXI4-Lite Master | DMA | PCIe to DMA Bypass |
| PCIe to DMA Bypass enabled | DMA | PCIe to DMA Bypass |
Different combinations of BARs can be selected. The tables above list only 32-bit selections and 64-bit selections for all BARs as an example. You can select different combinations of BARs based on your requirements.