Initial Debug of the XDMA - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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1.0 English

Status bits out of each engine can be used for initial debug of the subsystem. Per channel interface provides important status to the user application.

Table 1. Initial Debug of the Subsystem
Bit Index Field Description
6 Run Channel control register run bit.
5 IRQ_Pending Asserted when the channel has interrupt pending.
4 Packet_Done On an AXIST interface this bit indicates the last data indicated by the EOP bit has been posted.
3 Descriptor_Done A descriptor has finished transferring data from the source and posted it to the destination.
2 Descriptor_Stop Descriptor_Done and Stop bit set in the descriptor.
1 Descriptor_Completed Descriptor_Done and Completed bit set in the descriptor.
0 Busy Channel descriptor buffer is not empty or DMA requests are outstanding.