C2H Channel Performance Cycle Count (0xC8) - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. C2H Channel Performance Cycle Count (0xC8)
Bit Index Default Access Type Description
16 1’b0 RO

pmon_cyc_count_maxed

Cycle count maximum was hit.

15:10     Reserved
9:0 10’h0 RO

pmon_cyc_count [41:32]

Increments once per clock while running. See the Performance Monitor Control register (0xC0) bits Clear and Auto for clearing.