IRQ Block Channel Interrupt Pending (0x4C) - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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Table 1. IRQ Block Channel Interrupt Pending (0x4C)
Bit Index Default Access Type Description
[NUM_CHNL-1:0] ‘h0 RO


Engine Interrupt Pending.

One bit per read or write engine. This register indicates pending events. The pending events are cleared by removing the event cause condition at the source component. The position of the H2C bits always starts at bit 0. The position of the C2H bits is the index above the last H2C index, and therefore depends on the NUM_H2C_CHNL parameter.

The previous figure shows the packing of H2C and C2H bits.