Timing Constraint Rules for RLDRAM3 Signals

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2024-04-01

Revision

1.8 English

The following tables define timing constraints for various groups and their targets, similar to how they would be entered into PCB layout software tools. Adaptive SoC package delays should always be included for purposes of determining skews.

Table 1. Skew Constraint Rules for RLDRAM3 Signals (x18 Devices)¹
Skew Constraint	Pin Pair Set	Minimum (ps)	Maximum (ps)	Group	Target
Address/Command to Clock	Adaptive SoC to RLD3 device	–8	+8	A[20:0] BA[3:0] CS_B REF_B WE_B	CK
Data to DK0	Adaptive SoC to RLD3 device	–100	+100	DQ[8:0] DM0	DK0
Data to DK1	Adaptive SoC to RLD3 device	–100	+100	DQ[17:9] DM1	DK1
Data to QK0	Adaptive SoC to RLD3 device	–100	+100	DQ[8:0]	QK0
Data to QK1	Adaptive SoC to RLD3 device	–100	+100	DQ[17:9]	QK1
Data Write Clocks to Address/Command Clock	Adaptive SoC to RLD3 device	–110	+110	DK0 DK1	CK
Data Read Clocks to Address/Command Clock	Adaptive SoC to RLD3 device	-85	+85	QK0 QK1	CK
Clock²	Adaptive SoC to RLD3 device	0	2	CK CK_B	-
DK0²	Adaptive SoC to RLD3 device	0	2	DK0 DK0_B	-
DK1²	Adaptive SoC to RLD3 device	0	2	DK1 DK1_B	-
QK0²	Adaptive SoC to RLD3 device	0	2	QK0 QK0_B	-
QK1²	Adaptive SoC to RLD3 device	0	2	QK1 QK1_B	-
Include adaptive SoC package delays for all skew calculations. It does not matter which signal is faster or slower, but the difference in time between the two should be no longer than specified.

Table 2. Skew Constraint Rules for RLDRAM3 Signals (x36 Devices)¹
Skew Constraint	Pin Pair Set	Minimum (ps)	Maximum (ps)	Group	Target
Address/Command to Clock	Adaptive SoC to RLD3 device	–8	+8	BA[3:0] A[20:0] CS_B REF_B WE_B	CK
Data to DK0	Adaptive SoC to RLD3 device	–100	+100	A[20:0] DQ[8:0] DQ[26:18] DM0	DK0
Data to DK1	Adaptive SoC to RLD3 device	–100	+100	DQ[17:9] DQ[35:27] DM1	DK1
Data to QK0	Adaptive SoC to RLD3 device	–100	+100	DQ[8:0]	QK0
Data to QK1	Adaptive SoC to RLD3 device	–100	+100	DQ[17:9]	QK1
Data to QK2	Adaptive SoC to RLD3 device	–100	+100	DQ[26:18]	QK2
Data to QK3	Adaptive SoC to RLD3 device	–100	+100	DQ[35:27]	QK3
Data Write Clocks to Address/Command Clock	Adaptive SoC to RLD3 device	–110	+110	DK0 DK1	CK
Data Read Clocks to Address/Command Clock	Adaptive SoC to RLD3 device	-85	+85	QK0 QK1 QK2 QK3	CK
Clock²	Adaptive SoC to RLD3 device	0	2	CK CK_B	-
DK0²	Adaptive SoC to RLD3 device	0	2	DK0 DK0_B	-
DK1²	Adaptive SoC to RLD3 device	0	2	DK1 DK1_B	-
QK0²	Adaptive SoC to RLD3 device	0	2	QK0 QK0_B	-
QK1²	Adaptive SoC to RLD3 device	0	2	QK1 QK1_B	-
QK2²	Adaptive SoC to RLD3 device	0	2	QK2 QK2_B	-
QK3²	Adaptive SoC to RLD3 device	0	2	QK3 QK3_B	-
Include adaptive SoC package delays for all skew calculations. It does not matter which signal is faster or slower, but the difference in time between the two should be no longer than specified.