Quad SPI

Versal Adaptive SoC PCB Design User Guide (UG863)
Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English
  • PCB skew between QSPIx_IO[3:0] and QSPIx_CS_b lines relative to QSPIx_CLK should be within 50 ps.
  • For optimum performance, limit trace delays to 0.5 ns between the adaptive SoC and QSPI device.
  • Keep QSPI_LPBK_CLK (MIO[6]) unconnected for higher operating QSPIx_CLK frequencies (>37.5 MHz). This is mandatory for the loopback feature to operate properly (loopback is required for frequencies >37.5 MHz).
  • It is highly recommended to perform a signal integrity analysis on the QSPIx_CLK and QSPI_IO[0:3] lines for both read and write operations.
  • Place 4.7 kΩ pull-up resistors to VCCO_500 on the QSPIx_IO[3], Write Protect/QSPIx_IO[2], and QSPIx_CS_b lines. QSPIx_IO[3] is shared with HOLD, and QSPIx_IO[2] is shared with the Write Protect function.
  • Ensure proper signal integrity for traces:
    • There should be no reflections at the near and far end of the Versal device.
  • Ensure VIH/VIL and VOH/VOL levels are met for the Versal device:
    • Values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
    • Be sure to choose the correct levels for the voltage used (i.e., LVCMOS18, LVCMOS33).
  • For reads, ensure that the flash device drive strength matches the load (resistive + capacitive) being driven for optimal read performance:
    • This should especially be verified if adding series resistors on QSPI_CLK and/or QSPIx_IO[0:3] lines.
  • For the intended frequency of operation, ensure that setup and hold times are met for the Versal adaptive SoC and QSPI device.
  • Use the following formulas for determining if setup and hold times are met, and likewise to determine maximum QSPI frequency of operation:
    • Definitions:
      • Clock_Period = The clock period of the QSPI interface clock QSPI_CLK (1/FQSPI_CLK)
      • TQSPICKO_min/max = Versal adaptive SoC QSPI clock to output delay (see the Versal adaptive SoC data sheets)
      • TQSPIDCK = Versal adaptive SoC QSPI setup time (see the Versal adaptive SoC data sheets)
      • TQSPICKD = Versal adaptive SoC QSPI hold time (see the Versal adaptive SoC data sheets)
      • Tsetup (flash) = QSPI device setup time (see QSPI device datasheet)
      • Thold (flash) = QSPI device hold time (see QSPI device datasheet)
      • CTO_max (flash) = QSPI device data clock to output delay (see QSPI device datasheet)
      • Output_Hold (flash) = QSPI device output hold time before data begins changing (see QSPI device datasheet)
      • Max_PCB_trace_delay = The maximum PCB trace delay among QSPI_CLK, QSPIx_IO[0:3]
      • Min_PCB_trace_delay = The minimum PCB trace delay among QSPI_CLK, QSPIx_IO[0:3]
    • Formulas:
      • Write Setup/Hold (Data):
        • Tsetup (flash) ≤ Clock_Period – TQSPICKO_max – (skew between QSPI_CLK PCB trace delay and maximum QSPIx_[0:3] PCB trace delay)
        • Thold (flash) ≤ TQSPICKO_min – (skew between QSPI_CLK PCB trace delay and minimum QSPIx_[0:3] PCB trace delay)
          Note: See first bullet in this section regarding skew guidelines.
      • Read Setup/Hold (Data):
        • TQSPIDCK ≤ Clock_Period – CTO_max (flash) – 2*Max_PCB_trace_delay
        • TQSPICKD ≤ Output_Hold (flash) + 2 x Min_PCB_trace_delay
          Note: The 2X PCB trace delay in both equations is for round-trip time to/from the flash device.
      • Command Setup/Hold:
        • Tsetup (flash) ≤ Clock_Period – TQSPICKO_max – (skew between QSPI_CLK PCB trace delay and maximum QSPIx_[0:3] PCB trace delay)
        • Thold (flash) ≤ TQSPICKO_min – (skew between QSPI_CLK PCB trace delay and minimum QSPIx_[0:3] PCB trace delay)
          Note: See first bullet in this section regarding skew guidelines.