Physical Design Rules for LPDDR4/4x Signals

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2024-04-01

Revision

1.8 English

The following table defines routing rules for LPDDR4/4x signals.

Table 1. Physical Design Rules for LPDDR4/4x Signals
Parameter	Value
Impedance Rules
Impedance for single-ended CAC¹ and data signals	45Ω ±10%
Impedance for differential clock and data strobe signals	82Ω ±10%
Trace Length Rules (from Adaptive SoC to Furthest Device or Termination)
Maximum PCB trace length for CAC signals	3600 mil (route on inner signal layers only)
Maximum PCB trace length for data signals	3600 mil (route on inner signal layers no deeper than 45 mil from adaptive SoC)
Spacing Rules for CAC and Clock Signals
Minimum spacing between CAC signals within the same channel²	2H³, except: 1H under adaptive SoC or LPDDR4/4x device
Minimum spacing between CAC signals and clock signals within the same channel²	5H³, except: 2H under adaptive SoC or LPDDR4/4x device
Minimum spacing between CAC/clock signals and data/strobe signals within the same channel²	7H³, except: 2H under adaptive SoC or LPDDR4/4x device
Spacing Rules for Data and Data Strobe Signals
Minimum spacing between data signals within the same byte	2H³, except: 1H under adaptive SoC or LPDDR4/4x Device
Minimum spacing between data signals and data strobe signals within the same byte	5H³, except: 1H under adaptive SoC or LPDDR4/4x device
Minimum spacing between data/strobe signals between different bytes	7H³, except: 2H under adaptive SoC or LPDDR4/4x device
Minimum spacing between data/strobe signals and other signals within the same channel²	7H³, except: 2H under adaptive SoC or LPDDR4/4x device
Spacing Rules for Signals between Channels or Memory Interfaces
Minimum spacing between signals in one memory interface to signals in another channel or memory interface	7H³, except: 2H under adaptive SoC or LPDDR4/4x device
Maximum Vias per Signal
CAC signals and clock signals	2 each, except: 4 for signals touching more than one channel, such as with pin-efficient pinouts
CKE signals	3 each
Data and strobe signals	2 each
Other Physical Design Requirements
Do not route CAC/clock signals on more than one internal signal layer
Route all data/strobe signals with a byte on one internal signal layer
Route data/strobe signals on internal layers as close to the memory devices as possible
CAC stands for command/address/control. A channel is defined as either the “A” side of the LPDDR4/4x device or the “B” side of the LPDDR4/4x device. H is the distance to the nearest ground return plane.