PCB Routing Guidelines for HBM2e

This section provides PCB design guidelines for HBM2e interfaces. Because these memory interfaces are on-die, the PCB guidelines primarily center up input clocking and power-related items.

Versal Adaptive SoC HBM Reference Clock Connections (HBM_REF_CLK)

Each HBM stack in the Versal adaptive SoC contains one reference clock pair. The three selectable options for the input clocks are LVDS, LVCMOS, and internal clock. Different PCB connection options are required depending on the source of the reference clock.

The reference clock pin names are of the form C4CCIO_PAD0_800/801 and C4CCIO_PAD1_800/801, with 800 and 801 referring to the particular HBM stack on the device. PAD0 is the “P” side, while “PAD1” is the “N” side.

The following figures illustrate the PCB connection options for LVDS clocks, LVCMOS clocks, and when using the adaptive SoC internal clock option.

LVDS

Connect a 0.01 µF capacitor in series with the P and N pins, as shown in the following figure.

Figure 1. LVDS Routing Guidelines

LVCMOS

Connect the P input directly to the clock source while grounding the N input, as shown in the following figure.

Figure 2. LVCMOS Routing Guidelines

Internal Clock

When using the internal clock option, ground both the P and N inputs, as shown in the following figure.

Figure 3. Internal Clock Routing Guidelines

Powering HBM Stacks

HBM stacks should have their power rails connected even if any of them are not intended to be used.