The following table shows the required signals used in QDR-IV applications. Applications include 2x18 (36-bit) interfaces as well as 2x36 (72-bit) interfaces.
| Signal | Description | Required PCB Termination | Signal Routing Methodology |
|---|---|---|---|
| Clock Signals | |||
| CK_P/CK_N | Address/Command Clock | None, uses ODT | Point-to-Point |
|
DKA_P/N[1:0] DKB_P/N[1:0] |
Data Write Clock | None, uses ODT | Point-to-Point |
|
QKA_P/N[1:0] QKB_P/N[1:0] |
Data Read Clock | None, uses ODT | Point-to-Point |
| Address Signals | |||
|
A[21:0] (2x18, 36-bit) A[20:0] (2x36, 72-bit) |
Address | None, uses ODT | Point-to-Point |
| Command Signals | |||
| AP | Address Parity | None, uses ODT | Point-to-Point |
| AINV | Address Inversion | None, uses ODT | Point-to-Point |
| CFG_N | Mode Register Configuration | None, uses ODT | Point-to-Point |
|
LBK0_N LBK1_N |
Loopback Mode for Addr/Cmd/CK deskew | None, uses ODT | Point-to-Point |
|
LDA_N LDB_N |
Synchronous Load | None, uses ODT | Point-to-Point |
|
RWA_N RWB_N |
Synchronous Read/Write | None, uses ODT | Point-to-Point |
| Data Signals | |||
|
DQA[17:0] (2x18, 36-bit) DQB[17:0] (2x18, 36-bit) DQA[35:0] (2x36, 72-bit) DQB[35:0] (2x36, 72-bit) |
Data | None, uses ODT | Point-to-point |
|
QVLDA[1:0] QVLDB[1:0] |
Output Data Valid | None | Not Used |
| Miscellaneous Signals | |||
| RST_N | Reset | 4.7 kΩ to GND at far end | Pull-down |
| PE_N | Address Parity Error Output | None, direct connection | Point-to-point |
| QDR-IV Devices Only | |||
|
DINVA[1:0] DINVB[1:0] |
Data Inversion | Tie each to GND via 100Ω | Pull-down |
| ZQ_ZT | External Impedance | Tie 220Ω to GND | One per device |
| Adaptive SoC Only | |||
|
IO_VR_7xx IO_VR_8xx (if present) |
Calibration Reference |
240Ω to VCCO_7xx 240Ω to VCCO_8xx (if present) |
|
The following figure shows conceptual point-to-point routing for QDR-IV devices.
Figure 1. Point-to-Point Connections for QDR-IV Devices
