Adjusting for Different Stack-Ups

The trace width, spacing, length, and skew constraints presented in this chapter are based on the reference PCB materials listed in Reference Material Specifications. When not using these specific parameters, trace width, lengths, layer heights, spacings, and dielectric material could need adjustments to meet the impedance, length, and skew specifications.

The PCB fabrication house can adjust these factors to achieve the desired impedance and propagation delay targets. The effects of each of these items are listed in this section. In addition, a two-dimensional field solver utility allows for various combinations to be tested.

Dielectric Material

Each dielectric material has its own relative dielectric constant (D_K) and dissipation factor/loss tangent (D_F) that are contributing factors to line impedance (Z₀), signal propagation delay (T_PD), and signal loss (α). As D_K increases, impedance decreases while the signal propagation delay and signal loss increase, and vice versa. A typical D_K found on PCBs ranges from 3.4 to 4.6. The propagation delay in a given dielectric material is constant and is not affected by any other board parameters such as layer height, conductor width, or conductor spacing. Propagation delay is affected by frequency, but the effect is minimal with regards to typical memory speeds. Signal loss is also affected by frequency, with the loss increasing with increasing frequency.

The following equation shows the calculation for propagation delay (T_PD), with D_K as the dielectric constant, and c as the speed of light in free space (2.998 x 108 m/s or 1.180 x 1010 in/s).

The associations in the following table show the effect of the dielectric constant (D_K) on the impedance (Z₀), propagation delay (T_PD), and signal loss (α).

Trace Width

As the trace width (W) increases, the impedance decreases while the signal propagation delay remains unchanged, and vice versa. Any adjustments in width should include adjustments in spacing (S) to maintain immunity to crosstalk effects. Spacing factors are roughly 1.0X to 3X depending on the particular type of memory and signal. The associations in the following table show the effect of width on impedance, spacing, and propagation delay.

Layer Height

As the layer height (H) is increased, the impedance increases while the signal propagation delay remains unchanged, and vice versa. When reducing or increasing layer height, consider that layer heights that are too low can be more expensive to reliably manufacture because the PCB fabricator must avoid plane shorts. Layer heights that are too high can lead to aspect ratio violations. The associations in the following table show the effect of layer height on impedance and propagation delay.

Base Copper Weight

As the base copper weight (Cu oz) of the conducting lines is increased, the impedance decreases while the signal propagation delay remains unchanged, and vice versa. The most common base copper weight used in PCBs is 0.5, known as half-ounce copper. The effect of changing the base copper weight is minimal, however, and is not recommended due to the potential for increased costs in relation to the small benefit typically gained.

Example of Tuning Design Parameters to Meet Impedance Targets

The following table shows a target of 45Ω for stripline impedance in the main L1 PCB area. The trace width (W) is specified as 7.0 mils, DK of 3.71, and height of 6.7 mils. The table also shows tuning of the dielectric constant, trace width (W), and height (H) required to meet the impedance target. The spacing (S) shows how it should change in order to continue to meet performance requirements, though the spacing is not a factor in the line impedance. When increasing DK, the signal loss also increases as shown in the table.