PCB Design Features

The PCB guidelines in this document cover two primary areas:

• Power distribution:
  • Current step loads and device utilization
  • Recommended PCB decoupling capacitor quantities
  • Capacitor specification requirements
• Memory interface routing:
  • Required routing guidelines for all memory interfaces
  • DDR4
  • LPDDR4/4x
  • RLDRAM3
  • QDR-IV
• Schematic Design and Simulations Resources
  • Design Hub for PCB Board System Design
    • DDR4 and LPDDR4 Timing Models for HyperLynx DDRx Wizard in Versal Adaptive SoCs: This tutorial shows how to incorporate Versal adaptive SoC DDR4 and LPDDR4 timing models into HyperLynx.
    • Obtaining and Verifying Versal Adaptive SoC Memory Pinouts: This tutorial offers the fast method for obtaining valid memory pinouts from the AMD Vivado™ tools.
    • Versal Adaptive SoC Schematic Review Checklist (XTP546): Now includes an automated schematic checker.
    • Power Design Manager (PDM) tool (download at www.xilinx.com/power): Includes custom decoupling requirements based on the specific design.