Package Flight Time Differences

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
Release Date
1.8 English

Even if two devices across a given package are footprint compatible from a design and PCB standpoint, package flight times are different across different devices. This difference in package flight time should be accounted for to minimize the overall skew. Flight time information can be found within the AMD Vivado™ tools in the Package Pins tab during the I/O planning stage or after synthesis. The ideal strategy to account for pin flight time differences is to deskew the printed circuit board when migrating to the new device. If this is not possible, it is recommended to lay out the printed circuit board with the final device in mind to maximize system performance for the long term. System performance might have to be derated when using the initial device in certain scenarios. As a last option, choosing the mid-point of the range of flight times and routing the board based on that value can act as a compromise, though maximum system performance might not be achievable with this method in certain scenarios.


Pin flight time information can be obtained from the Package Pins tab within the Vivado tools, both in the I/O planning stage and after synthesis.

Figure 1. Vivado Example Showing Pin Flight Times