SPI

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2024-04-01

Revision

1.8 English

Skew between SPIx_MISO/SPIx_MOSI and SPIx_CLK should be within 100 ps.
Place a 4.7 kΩ pull-up resistor on the SS pin near the serial peripheral interface (SPI) device.
For all frequencies, ensure setup and hold times are met for the Versal adaptive SoC and SPI device, depending on master/slave configuration.
To verify setup and hold times are met, and to determine maximum operating frequency, refer to the formulas below:
- Definitions:
  - Clock_Period = The clock period of the SPI interface clock SPI_CLK (1/F_{MSPI_CLK} or 1/F_{SSPI_CLK})
  - T_MSPICKO max/min = Versal adaptive SoC MOSI SPI Clock to Output Delay (master)
  - T_SSPICKO max/min = Versal adaptive SoC MOSI SPI clock to output delay (slave)
  - T_MSPIDCK = Versal adaptive SoC SPI setup time (master)
  - T_MSPICKD = Versal adaptive SoC SPI hold time (master)
  - T_SSPIDCK = Versal adaptive SoC SPI setup time (slave)
  - T_SSPICKD = Versal adaptive SoC SPI hold time (slave)
  - CTO min/max (flash) = SPI device clock to output delay (see SPI device datasheet)
  - Tsetup (flash) = SPI device setup time (see SPI device datasheet)
  - Thold (flash) = SPI device hold time (See SPI device datasheet)
  - Max_PCB_trace_delay = The maximum PCB trace delay among SPI_CLK, SPIx_MOSI (Master Mode), or SPI_CLK, SPIx_MISO (slave mode)
  - Min_PCB_trace_delay = The minimum PCB trace delay among SPI_CLK, SPIx_MOSI (Master Mode), or SPI_CLK, SPIx_MISO (slave mode)
- Formulas:
  - Master Mode
    - Write:
      - Tsetup (flash) ≤ Clock_Period – T_MSPICKO max – (skew between SPI_CLK PCB trace delay and SPIx_MOSI PCB trace delay)
      - Thold (flash) ≤ T_MSPICKO min – (skew between SPI_CLK PCB trace delay and SPIx_MOSI PCB trace delay)
        Note: See the first bullet in this section regarding skew guidelines.
    - Read:
      - T_MSPIDCK ≤ Clock_Period – CTO max (flash) – 2 x Max_PCB_trace_delay
      - T_MSPICKD ≤ CTO min (flash) + 2 x Min_PCB_trace_delay
        Note: The 2X PCB trace delay in both equations is for round-trip time to/from the flash device.
  - Slave Mode
    - Write:
      - T_SSPIDCK ≤ Clock_Period – CTO max (flash) – (skew between SPI_CLK PCB trace delay and SPIx_MOSI PCB trace delay)
      - T_SSPICKD ≤ CTO min (flash) + 2 x Min_PCB_trace_delay
        Note: See the first bullet in this section regarding skew guidelines.
        
        Note: The 2X PCB trace delay in both equations is for round-trip time to/from the flash device.
    - Read:
      - Tsetup (SPI/Master) ≤ Clock_Period – CTO max (Versal adaptive SoC) – 2 x Max_PCB_trace_delay
      - Thold(SPI/Master) ≤ CTO min(Versal adaptive SoC) + 2 x Min_PCB_trace_delay
      - NOTE: The 2X PCB trace delay in both equations is for round-trip time to/from the flash device.
Ensure proper signal integrity on the PCB:
- No reflections at near or far end of Versal device
- Ensure V_IH/V_IL and V_OH/V_OL levels are met for both the Versal and flash devices.
  - Values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
    - Be sure to choose the correct levels for the voltage used (i.e., LVCMOS18, LVCMOS33).