This chapter lists PCB layout guidelines specific to the PS/PMC multiplexed I/O (MIO) and GTY/GTYP transceiver interfaces in AMD Versal™ adaptive SoCs.
Important: Refer to
Versal
Adaptive SoC Technical Reference Manual (AM011) for architectural
descriptions of each peripheral interface listed in this chapter.
Important: All GTY/GTYP
transceiver interfaces mentioned in this chapter refer to
Versal
Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).