Signals and Connections for LPDDR4/4x Interfaces

Versal Adaptive SoC PCB Design User Guide (UG863)
Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English

The required signals used in LPDDR4/4x applications are shown in the following table.

Table 1. LPDDR4/4x Signal Definitions
Signal Description Required PCB Termination
Clock Signals
CK_T[C]_A, CK_T[C]_B Address/Command clock None, uses ODT 48Ω
Command/Address Signals
CA[5:0]_A, CA[5:0]_B Address None, uses ODT 48Ω
Control Signals
CS0_A, CS0_B Chip Select None, uses ODT 48Ω
CS1_A, CS1_B Chip Select (dual rank only) None, uses ODT 48Ω
LPDDR4: CKE0_A, CKE0_B

LPDDR4: CKE1_B, CKE1_B

(dual rank only)

 Clock Enable 160Ω to GND/160Ω to VDD2 (1.1V) (see Figure 1)
LPDDR4X: CKE0_A, CKE0_B

LPDDR4X: CKE1_B, CKE1_B

(dual rank only)

 Clock Enable

160Ω to GND/160Ω to VDD2 (1.1V) (see Figure 1)

OR

160Ω to VDDQ (0.6V) (see Figure 1)
Note: If terminating to VDDQ, ensure VDDQ rail can sink current.
Data Signals
DQ[15:0]_A, DQ[15:0]_B Data None, uses ODT 48Ω
DM[1:0]_A, DM[1:0]_B (if present) Data Mask None, uses ODT 48Ω
Data Strobe Signals
DQS[1:0]_T[C]_A, DQS[1:0]_T[C]_B Differential Data Strobe None, uses ODT 48Ω
Miscellaneous Signals
RESET_n Reset (one per LPDDR4/4x device) 4.7 kΩ to GND
LPDDR4/4x Device Only
LPDDR4: ODT_A, ODT_B On Die Termination Control

(per device)

 Direct to VDD2 (except for ODT_A on 2x32 pin efficient, see Figure 7).
LPDDR4x: ODT_A, ODT_B On Die Termination Control

(per device)

 Direct to VDD2
ZQ0 Calibration Reference (per device) 240Ω to VDDQ
ZQ1 Calibration Reference

(per device, dual rank only)

 240Ω to VDDQ
Adaptive SoC Only

IO_VR_7xx

IO_VR_8xx (if present)

 Calibration Reference

240Ω to VCCO_7xx

240Ω to VCCO_8xx (if present)
  1. Unused inputs to LPDDR4 ECC devices can be grounded through a common 100Ω resistor.
Figure 1. LPDDR4/4X CKE Termination
Note: If terminating CKE to VDDQ (0.6V), ensure that the VDDQ rail can sink current.

Supply Voltage Differences between LPDDR4 and LPDDR4x

Users should be aware of the varying voltages levels for the adaptive SoC and memory devices between LPDDR4 and LPDDR4x, as shown in the following table.

Table 2. Typical Supply Voltages for LPDDR4 and LPDDR4x
Interface VCCO_xxx (Adaptive SoC) VDD2 VDDQ
LPDDR4 1.1V 1.1V 1.1V
LPDDR4x 1.2V 1.1V 0.6V
Important: If it is desired to power down the LPDDR4 device(s) while maintaining adaptive SoC power, the adaptive SoC VCCO 1.1V supply and 1.1V LPDDR4 VDDQ supply should be separated and controlled appropriately.

The following figures show the various supported connection options for LPDDR4/4x such as 2x32, 1x32 with and without ECC, 2x16, 1x16, and pin efficient 2x32 and 1x32 that use significantly fewer adaptive SoC pins than the regular 2x32 and 1x32 options.

Figure 2. Connections for a 2x32 LPDDR4/4x Interface
Figure 3. Connections for a 1x32 (or x48) with ECC LPDDR4/4x Interface
Figure 4. Connections for a 1x32 LPDDR4/4x Interface
Figure 5. Connections for a 2x16 LPDDR4/4x Interface
Figure 6. Connections for a 1x16 LPDDR4/4x Interface
Figure 7. Connections for a Pin Efficient 2x32 LPDDR4/4x Interface
Figure 8. Connections for a Pin Efficient 1x32 LPDDR4/4x Interface