This involves high-frequency noise on one rail in the adaptive SoC moving out of the adaptive SoC through its BGA balls and onto the combined plane, where it travels back into the adaptive SoC via the BGA balls of the other plane. For example, clock buffer circuitry in Versal devices is powered via the VCC_RAM rail. Excessive high-frequency noise on VCC_RAM in the adaptive SoC can travel to VCCINT by way of the PCB. For low-frequency noise, the on-die capacitors and PCB bypass capacitors (in proper quantity) are extremely effective at mitigation.
Mitigating Self-Induced High-Frequency Noise from VCC_RAM to VCCINT
Do not excessively turn on/off the block RAM cells in the adaptive SoC (usually via clock buffers), as this can lead to large current spikes on VCC_RAM. In general, typical block RAM reads and writes do not generate excessive noise, so this type of activity does not require mitigation.
Extra PCB bypass capacitors might not be enough to mitigate the effect of high-frequency self-generated noise, because the PCB capacitors can take too long to respond. The most effective self-induced noise mitigation comes from within the actual user design itself.
Mitigating Self-Induced High-Frequency Noise from VCCINT to VCC_RAM
Keep periodic large current spikes to a minimum. This can be accomplished by design pipelining and/or staged turning on and off of various circuit blocks. Avoid operating VCCINT circuitry at or near resonance because it is very difficult to mitigate this noise even with many extra bypass capacitors.
Extra PCB bypass capacitors might not be enough to mitigate the effect of high-frequency self-generated noise because the PCB capacitors can take too long to respond. The most effective self-induced noise mitigation comes from within the actual user design itself.