SelectMAP

General Board Design Guidelines for the SelectMAP Bus

• Skew between SMAP_IO[31:0] and SMAP_CLK signals should be within ± 25 ps.
• Do not leave SMAP_CLK floating or held between VIL and VIH.
• SMAP_CLK is a critical signal. Ensure signal integrity is good on this signal.
• Connect SMAP_CS_b to a 4.7 kΩ pull-up to ensure the Versal device SelectMAP is deselected during power-up and microprocessor initialization.
• Connect SMAP_RDWR_b to a 4.7 kΩ pull-down to ensure the SelectMAP target defaults to the write direction during power-up and microprocessor initialization.
• Drive POR_B with an open-drain driver if using POR_B to reset/clear the Versal device configuration.
  • For example, the controller should not drive POR_B High because other devices can drive POR_B Low.
• Ensure VIH/VIL and VOH/VOL levels are met for the Versal device
  • Values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
  • Be sure to choose the correct voltage levels for the voltages used (LVCMOS18, LVCMOS33).

Multiple, Independent Target Device SelectMAP Board Design Guidelines

• The controller should have individual SMAP_BUSY pins for each target.
• The controller should have individual SMAP_CS_b pins for each target.
• The controller should have individual SMAP_RDWR_b signals for each target.
• If the controller monitors DONE, it should "AND" together the individual DONE lines from each target.
• If the controller monitors ERROR_OUT, it should monitor the ERROR_OUT of each target individually, or "OR" together the individual ERROR_OUT lines from each target.
• For advanced use cases, the Ganged SelectMAP setup for parallel write cannot support readback.