Timing Constraint Rules for DDR4 Signals

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2024-04-01

Revision

1.8 English

The timing constraints are defined in the following tables for various signal groups and their targets, similar to how they would be entered into PCB layout software tools. Adaptive SoC package delays should always be included for purposes of determining skews.

Table 1. Skew Constraint Rules for DDR4 Signals (Components)¹
Skew Constraint	Pin Pair Set	Minimum (ps)	Maximum (ps)	Group	Target
Address to Clock²	Adaptive SoC to DDR4 component	–34	–50	A[17], A[13:0] RAS_N/A[16] CAS_N/A[15] WE_N/A[14] BA[1:0] BG[1:0] ACT_N CKE CS_N ODT PAR	CK_T
Clock^2,3	Adaptive SoC to DDR4 component	0	2	CK_T CK_C	-
Data to DQS⁴	Adaptive SoC to DDR4 component	–100	+100	DQ (4/8 bits) DM/DBI (if present)	DQS_T
DQS^3,4	Adaptive SoC to DDR4 component	0	2	DQS_T DQS_C	-
Clock to DQS⁴	Adaptive SoC to DDR4 component	–149	+1796	CK_T	DQS_T
Include adaptive SoC package delays for all skew calculations. There should be individual constraint sets for each DDR4 component (for example, adaptive SoC to DRAM 1, adaptive SoC to DRAM 2, etc.). It does not matter which signal is faster or slower, but the difference in time between the two should be no longer than specified. There should be individual constraint sets for each byte/nibble/DQS pair.

Table 2. Skew Constraint Rules for DDR4 Signals (DIMM)¹
Skew Constraint	Pin Pair Set	Minimum (ps)	Maximum (ps)	Group	Target
Address to Clock²	Adaptive SoC to DIMM	–8	+8	A[17], A[13:0] RAS_N/A[16] CAS_N/A[15] WE_N/A[14] BA[1:0] BG[1:0] ACT_N CKE CS_N ODT PAR	CK_T
Clock^2,3	Adaptive SoC to DIMM	0	2	CK_T CK_C	-
Data to DQS⁴	Adaptive SoC to DIMM	–100	+100	DQ (4/8 bits) DM/DBI (if present)	DQS_T
DQS^3,4	Adaptive SoC to DIMM	0	2	DQS_T DQS_C	-
Clock to DQS⁴	Adaptive SoC to DIMM	–150	+150	CK_T	DQS_T
Include adaptive SoC package delays for all skew calculations. There should be individual constraint sets for each DDR4 DIMM (for example, adaptive SoC to DIMM 1, adaptive SoC to DIMM 2, etc.). It does not matter which signal is faster or slower, but the difference in time between the two should be no longer than specified. There should be individual constraint sets for each byte/nibble/DQS pair.