The required signals used in RLD3 applications are shown in the following table. Signal options are shown for both 36-bit and 18-bit RLD3 devices.
| Signal | Description | Required PCB Termination | Signal Routing Methodology |
|---|---|---|---|
| Clock Signals | |||
| CK/CK_B | Address/Command Clock | See Figure 2 | Fly-by |
| DK/DK_B[1:0] | Data Write Clock | None, uses ODT | Point-to-Point |
|
QK/QK_B[3:0] (36-bit) QK/QK_B[1:0] (18-bit) |
Data Read Clock | None, uses ODT | Point-to-Point |
| Address Signals | |||
| A[20:0] | Address | 39Ω to VTT at far end | Fly-by |
| BA[3:0] | Bank Address | 39Ω to VTT at far end | Fly-by |
| Command/Control Signals | |||
| CS_B | Chip Select | 39Ω to VTT at far end | Fly-by |
| REF_B | Refresh | 39Ω to VTT at far end | Fly-by |
| WE_B | Write Enable | 39Ω to VTT at far end | Fly-by |
| Data Signals | |||
|
DQ[35:0] (36-bit) DQ[17:0] (18-bit) |
Data | None, uses ODT | Point-to-point |
| DM[1:0] | Data Mask | None, uses ODT | Point-to-point |
| QVLD/QVLD[1:0] | Data Valid | None | Not used |
| Miscellaneous Signals | |||
| RESET_B | Reset | 4.7 kΩ to GND at far end | Fly-by |
| RLD3 Devices Only | |||
| ZQ | External Impedance | 240Ω to GND | One per memory device |
| MF | Mirror Function | Direct to GND or through 0Ω resistor for fly-by. See Figure 1 for clamshell. | One per memory device or shared fly-by |
| Adaptive SoCs Only | |||
|
IO_VR_7xx IO_VR_8xx (if present) |
Calibration Reference |
240Ω to VCCO_7xx 240Ω to VCCO_8xx (if present) |
|
A common usage for RLDRAM3 is a x72 architecture composed of two x36 RLD3 devices. The following figures show the connections for clamshell and fly-by configurations, respectively.
Figure 1. Clamshell RLDRAM3 Memory with Width Expansion
Figure 2. Fly-by RLDRAM3 Memory with Width Expansion
