The following table defines timing constraints for various signal groups and their targets, similar to how they would be entered into PCB layout software tools. Adaptive SoC package delays should always be included for purposes of determining skews.
| Skew Constraint | Pin Pair Set | Minimum (ps) | Maximum (ps) | Group | Target |
|---|---|---|---|---|---|
| Address to Clock A | Adaptive SoC to LPDDR4/4x Device | –100 | +100 | CA[5:0]_A | CK_T_A |
| Address to Clock B | Adaptive SoC to LPDDR4/4x Device | –100 | +100 | CA[5:0]_B | CK_T_B |
| Command to Clock A | Adaptive SoC to LPDDR4/4x Device | –20 | +20 |
CKE0_A CKE1_A 2 CS0_A CS1_A 2 |
CK_T_A |
| Command to Clock B | Adaptive SoC to LPDDR4/4x Device | –20 | +20 |
CKE0_B CKE1_B 2 CS0_B CS1_B 2 |
CK_T_B |
| Clock (A or B) 3 | Adaptive SoC to LPDDR4/4x Device | 0 | 2 |
CK_T_A/B CK_C_A/B |
- |
| Data to DQS0 | Adaptive SoC to LPDDR4/4x Device | –100 | +100 |
DQ[7:0] DM0 |
DQS0_T |
| Data to DQS1 | Adaptive SoC to LPDDR4/4x Device | –100 | +100 |
DQ[15:8] DM1 |
DQS1_T |
| Data to DQS2 | Adaptive SoC to LPDDR4/4x Device | –100 | +100 |
DQ[23:16] DM2 |
DQS2_T |
| Data to DQS3 | Adaptive SoC to LPDDR4/4x Device | –100 | +100 |
DQ[31:24] DM3 |
DQS3_T |
| DQS0 3 | Adaptive SoC to LPDDR4/4x Device | 0 | 2 |
DQS0_T DQS0_C |
- |
| DQS1 3 | Adaptive SoC to LPDDR4/4x Device | 0 | 2 |
DQS1_T DQS1_C |
- |
| DQS2 3 | Adaptive SoC to LPDDR4/4x Device | 0 | 2 |
DQS2_T DQS2_C |
- |
| DQS3 3 | Adaptive SoC to LPDDR4/4x Device | 0 | 2 |
DQS3_T DQS3_C |
|
| DQS0 to Clock A 3 | Adaptive SoC to LPDDR4/4x Device | –150 | +150 | DQS0_T | CK_A |
| DQS1 to Clock A 3 | Adaptive SoC to LPDDR4/4x Device | –150 | +150 | DQS1_T | CK_A |
| DQS2 to Clock B 3 | Adaptive SoC to LPDDR4/4x Device | –150 | +150 | DQS2_T | CK_B |
| DQS3 to Clock B 3 | Adaptive SoC to LPDDR4/4x Device | –150 | +150 | DQS3_T | CK_B |
|
|||||