Revision History

The following table shows the revision history for this document.

Section	Revision Summary
04/01/2024 Version 1.8
Table 1	Added VCCO_8xx to list of power rails.
Unused VCCO Banks and NC Pins	Added sentence about NC pins. Updated rules for powering XPIO banks.
Limitations of Sense Lines	Added paragraph to discuss simulation. Added section on managing sense lines with multiple connected rails.
Routing Under Land-Side Capacitors	Updated description of plane under LSC area.
Table 1	Updated rules for ALERT_N connections. Replaced IO_VR_700 with IO_VR_7xx, and IO_VR_800 with IO_VR_8xx.
Table 1, Table 1, and Table 1	Replaced IO_VR_700 with IO_VR_7xx, and IO_VR_800 with IO_VR_8xx.
PMC Dedicated Pins	Removed redundant bullet about selecting SSI technology devices.
Octal SPI	Removed "for production silicon" from skew bullet.
09/14/2023 Version 1.7
Table 1	Added row for VCCO_503/510/520/530.
Routing Under Land-Side Capacitors and Noise Mitigation Strategies when Combining VCCINT and VCC_RAM	Added new sections.
PCB Guidelines for Memory Interfaces	Added HBM2e to list of memory architectures.
Required Memory Routing Guidelines for All Interfaces	In guideline 5, updated description of assumed drive strength and added link to answer record. Clarified guideline 6 to explain that it only applies when LVDS is the input standard for the system clock.
Signals and Connections for LPDDR4/4x Interfaces	Added note to Table 1. Added important note about separating 1.1V rails. Removed ZQ1 from Figure 7 and Figure 8.
PCB Routing Guidelines for HBM2e	Added new section.
GTY/GTYP Transceiver Interfaces	Added guidance for PCIe and HSDP.
PMC Dedicated Pins	Removed sentence about number of dedicated I/O. Added pull-up information for PUDC_B. Added rules for VCC_BATT and VCC_FUSE pins.
I2C	Removed mention of I3C.
Octal SPI	Removed ES1 skew guidelines.
12/14/2022 Version 1.6
General updates	Replaced references to XPE with the PDM tool.
Table 1	Added HBM series power rails and table note.
Unused VCCO Banks and NC Pins	Added HDIO to the group of banks that can be grounded if unused.
Recommended Decoupling Capacitor Quantities for Versal Devices	Updated first paragraph.
Target Impedance	Added link to PDN models.
Adaptive SoCs with Dedicated Sense Pins	Added important note about reserved sense pins.
Required Memory Routing Guidelines for All Interfaces	Added sentence about DQS_BIAS in place of the circuitry in item 6.
Utilizing Address Mirroring to Ease Clamshell Routing	Added section.
PMC Dedicated Pins	Added guidance for devices with multiple sets of POR_B, MODE[3:0], and PUDC_B pins.
Versal Adaptive SoC Migration Checklist	Added GTYP fabric access limitations and GT_RCAL and GT_RREF pin differences.
Reserved Sense Lines	Added section.
10/19/2022 Version 1.5
Required Memory Routing Guidelines for All Interfaces	Added guideline 17.
Reference Material Specifications	Updated board thickness.
I3C and I2C	Added I3C.
06/15/2022 Version 1.4
Table 1	Extensive updates to table.
PMC Dedicated Pins	Updated section.
CAN FD, I3C and I2C, Trace Port Interface Unit, Triple Time Counter, UART, System Windowed Watchdog Timer	Added bullet for V_IHV_ILand V_OH/V_OL levels.
Quad SPI	Changed QSPI read hold equation to contain Output_Hold as a parameter instead of CTO_min (flash).
SelectMAP	Added topic.
Differences in XPIO Performance	Updated maximum data rate from 3200 Mb/s to 3733 Mb/s.
Material Properties and Insertion Losses	Added appendix.
04/27/2022 Version 1.3
Table 1	Added VCC_FUSE and VCC_BATT. Changed voltage for GTYP_AVCC and GTM_AVCC to 0.92V.
Clamshell Topology	Added section.
PMC Dedicated Pins	Added bullet about JTAG boot mode. Added bullet for devices using multiple reference clocks.
Gigabit Ethernet MAC 10/100/1000 RGMII, Octal SPI, Quad SPI, SD/SDIO/eMMC, SPI, USB 2.0	Updated sections.
02/01/2022 Version 1.2
Current Step Load Assumptions	Updated to specify that only VCCINT is adjustable.
Voltage Ripple Assumptions	Added definition of AC voltage ripple.
Target Impedance	Removed frequency range and added reference to XPE.
Planar Resistance Recommendations and PCB Routing for Remote Voltage Sense Lines	Added new sections.
PCB Routing Guidelines for LPDDR4/4x Interfaces	Updated note.
Table 1	Updated PCB termination for CKE0_A, CKE0_B, CKE1_B, and CKE1_B.
Figure 1	Changed LPDD4 termination to VDD2 (1.1V).
Table 1	Updated maximum PCB trace length for CAC and data signals to 3600 mil.
PMC Dedicated Pins, Gigabit Ethernet MAC 10/100/1000 RGMII, Octal SPI, SD/SDIO/eMMC, SPI, and USB 2.0	Updated sections.
Quad SPI	Updated section and removed QSPI Board Delay Guidelines table.
GTYP Transceiver Fabric Access Limitations and GT_RCAL and GT_RREF Differences	Added new sections.
Default Capacitor Quantities for Versal Devices	Removed appendix.
07/01/2021 Version 1.1
PCB Design Features	Added bullet on schematic design and simulations resources.
Table 1	Updated voltages for VCC_PMC and VCCO. Updated power rails for GTY, GTYP, and GTM transceivers.
Unused VCCO Banks and NC Pins	Added new section.
Power Management Scenarios	Updated section and removed individual power management sections.
Required Memory Routing Guidelines for All Interfaces	In guideline 12, updated capacitor value from 1.0 μF to 0.1 μF. Added figures to guideline 15.
Reference Material Specifications	Changed board material from FR4 to Megtron 6 class. Changed dielectric constant from 4.0 to ~3.7. Changed dissipation factor from 0.023 to 0.002. Added layer order.
Adjusting for Different Stack-Ups	Added new section.
Signals and Connections for DDR4 Interfaces	Updated Table 1 and added important note.
PCB Routing Guidelines for DDR4 Interfaces, PCB Routing Guidelines for LPDDR4/4x Interfaces, PCB Routing Guidelines for RLDRAM3 Interfaces, and PCB Routing Guidelines for QDR-IV Interfaces	Added important note.
Table 1	Updated maximum PCB trace length for CAC and trace signals to 3000 mil.
Table 1	Updated table.
PMC Dedicated Pins	Added bullet about connecting MODE pins to VCCO_503.
Octal SPI	Added bullet about placing 4.7–10 kΩ pull-up resistors to VCCO_503.
Quad SPI	In the fourth bullet, changed VCCO_503 to VCCO_500.
Migration between Versal Devices and Packages	Updated device numbers. Added GTYP transceivers. Removed last paragraph.
Versal Adaptive SoC Migration Checklist	Updated section.
Footprint Compatibility between Packages	Updated device numbers and packages.
Differences in XPIO, HDIO, and Transceiver Count	Updated section, including Figure 1.
Package Dimensions	Updated Example section.
VCCSDFEC Rail	Updated section.
VCCINT_GT_L/R Rail, VCC_CPM5 Rail, GTY Transceiver Fabric Access Limitations, and VCC_IO and IO_VR Pin Differences	Removed sections.
Differences in Transceiver Counts	Updated section and removed example.
Differences in XPIO Performance	Updated device numbers and packages.
XPIO Bank Fabric Access Limitations	Updated first paragraph and Figure 1.
I/O Bank and GT Quad Number Differences	Updated section, including Figure 1.
Table 25	Moved VCC_PMC to VCCINT column.
Minimum Rails, Low Voltage, PS Overdrive	Moved VCC_PMC from Table 26 to Table 27.
Table 31 and Table 32	Removed voltage values from table headings.
11/24/2020 Version 1.0
Initial release.	N/A