Target Impedance

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2024-04-01

Revision

1.8 English

Given the required ripple tolerance and step load amount, a target impedance can be calculated. The impedance of the PDN network on the board should be targeted to be at or below this target impedance at the typical frequency in which decoupling capacitors are most effective (see the PDM tool for frequency ranges). Beyond these frequencies, the internal and mounting inductances of the capacitors reduce their effectiveness.

The formula for target impedance is shown in the following equation.

Figure 1. Target Impedance Equation

An example calculation for a 0.80V rail specified with ±3% tolerance (1% DC, 2% AC) and 40A of required step current is as follows:

Figure 2. Target Impedance Calculation

Recall that ±2% is used as the ripple target because ±1% is assumed to be taken by the tolerance of the VRM.

Note: For the case where the ripple tolerance is given as a fixed number such as 17 mV, use the fixed value as the numerator in the above equation.

Tip: AMD recommends running a full board-level PDN simulation to confirm that the voltage specifications are met. PDN models can be downloaded at https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/pdn-models/versal-acaps.html.