Required Memory Routing Guidelines for All Interfaces

Include package delay in routing constraints when determining signal trace lengths unless otherwise specified. When minimum and maximum values are available for the package delay, use the midpoint/average between the minimum and maximum values. Package delays can be found in the Vivado tools by opening an elaborated design and using File > Export > Export I/O Ports and checking the CSV file option.

DQ and DQS signals in the same byte group should be routed on the same layer from Versal device to DRAM/DIMM. Include the data mask (DM) in the byte group as applicable.

Do not change layers when routing from one DIMM to the next for multi-slot topologies. Additionally, it is recommended to route data byte groups on the highest signal layers (closest to the DIMM connector) as much as possible. Depending on the DIMM placement, the longest DQ bytes could be the center ones or the edge ones.

For fly-by routing, address, command, and control signals can be routed on different layers, but it is recommended to use as few as possible. Do not route any individual signal on more than two layers to minimize inductive loops that can lead to crosstalk issues. Any signal layer switching via needs to have one ground via within a 50 mil radius.

Timing constraint specifications in this chapter are presented in several forms. The first form is where a group of signals have a minimum and maximum delay with regards to a target signal. Each signal in the group must have a relative delay to the target within the minimum and maximum values specified. An example for DDR4 DQ to DQS is shown in the following figure. Each DQ signal in the group must have a skew between –100 ps to 100 ps relative to the DQS target.

Figure 1. Skew Example for DQ to DQS

Note that the “shortest” and “longest” specifications can both be negative, as in the case of DDR4 address to clock. That specification requires that both the minimum and maximum skews relative to the clock must be negative (i.e., the clock trace is always longer than the address traces). The example representation of this is shown in the following figure.

Figure 2. DDR4 Address to Clock

Differential clock and DQS constraints do not list a target and should have the specified skews relative to the “P/N” (or T/C) pairs. The maximum skew between P/N (T/C) signals should be no greater than the “maximum” specification, as shown in the following figure.

Figure 3. Skew Example for Clock Signals

The final specification type refers to the CK to DQS specification for DDR4, which states that the CK to DQS specification for each memory device can range from CK having a skew of –149 ps to the DQS up to +1,796 ps. Typically, the absolute value of the skew would be smaller for the memory devices closer to the Versal device, and larger for the memory devices furthest from the Versal device. An example representation is shown in the following figure.

Figure 4. Interpretation of CK to DQS Skew Specification

Versal device and memory drive strengths can vary based on the interface and topology. Refer to Answer Record 76059 for details on DDR4, LPDDR4, and LPDDR4x.

If the system clock is connected to a bank that is also used for memory interfaces, the incoming clock signals must be biased so that they adhere to the signal level requirements of the I/O standard in the bank. Refer to the "AC Coupling Recommendations" section in Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) for specific requirements, as well as Answer Record 76062. The following figure shows the biasing structure from those reference documents for a DDR4 use case. AMD also recommends using DQS_BIAS with the unpopulated bias circuitry in place as a fallback option.

Figure 5. AC-Coupled with DC-Biased Differential Clock Input

Signal lines must be routed over a solid reference plane. Avoid routing over voids, as shown in the following figure.

Figure 6. Signal Routing Over Solid Reference Plane

Avoid routing over reference plane splits, as shown in the following figure.

Figure 7. Signal Routing Over Reference Plane Split

Keep the routing at least 30 mils away from the reference plane and void edges with the exception of breakout regions, as shown in the following figure.

Figure 8. Breakout Region Routing

Use chevron-style routing to allow for ground stitch vias. Figure 9 shows recommended routing for fly-by configurations, while Figure 10 shows recommended routing to accommodate ground stitch vias in a more congested clamshell configuration.

Figure 9. Example of Ground Stitching (Fly-by)

Figure 10. Example of Ground Stitching (Clamshell) Red: Power, Green: Ground

The following figure shows simulated eye diagrams for a DDR4 command/address/control bit with and without ground stitching vias. The simulation on the left shows an eye height of 180 mV with ground stitch vias, while the simulation on the right shows an eye height of only 99 mV when not utilizing ground stitch vias.

Figure 11. Simulations With and Without Ground Stitching Vias

Add ground vias as much as possible around the edges and inside the device (adaptive SoC, memory component, DIMM) to make a better ground return path for signals and power, especially corners. Corner or edge balls are generally less populated as grounds.

For address/command/control VTT termination (DDR4 only), every four termination resistors should be accompanied by one 0.1 μF capacitor, physically interleaving among resistors, as shown in the following figure. Refer to the memory vendor’s data sheet for specifications regarding noise limits on the address/command/control VTT lines.

Figure 12. Schematic Example of VTT Resistor and Capacitor Connections (DDR4 Only)

Figure 13. Example of V_TT Termination Placement (DDR4 Only)

For DIMM topologies, place bypass capacitors near the command/address/control pads to provide extra ground via locations. These bypass capacitors also provide a lower impedance path from power to ground. This is important because the address/command/control pins are referenced to ground on the adaptive SoC and PCB while they are referenced to power on the DIMM.

For dual-slot DIMM topologies, place DIMM #0 on the furthest connector from the adaptive SoC to reduce the effect of SI reflections. The DIMM #1 connector should be placed nearest to the adaptive SoC.

For interfaces with two copies of the clock and nine or more components (for example, interfaces with dual-die package (DDP) devices), it is recommended to route the clocks in an alternating pattern such that clock 1 connects to devices 1, 3, 5, 7, etc., and clock 2 connects to devices 2, 4, 6, 8, etc. All terminations should be placed at the end of the fly-by topology.

Figure 14. DDR4 2CK Single-Rank Configuration

Figure 15. DDR4 2CK Dual-Rank Configuration

For clamshell configurations that use address mirroring, ensure that both chip select lines have adequate decoupling at their terminations as well as sufficient plane/trace thicknesses to/from VTT.

Ensure that all PCB traces are within a 50 mil radius from a ground via to ensure impedance continuity through the PCB.

Figure 16. Ground Via Radius

Required Memory Routing Guidelines for All Interfaces - UG863

Versal Adaptive SoC PCB Design User Guide (UG863)