Required Memory Routing Guidelines for All Interfaces

The following list contains guidelines that apply to all memory interfaces (DDR4, LPDDR4/4x, RLD3, and QDR-IV interfaces).

1. Include package delay in routing constraints when determining signal trace lengths unless otherwise specified. When minimum and maximum values are available for the package delay, use the midpoint/average between the minimum and maximum values.
2. DQ and DQS signals in the same byte group should be routed on the same layer from Versal device to DRAM/DIMM. Include the data mask (DM) in the byte group as applicable.
3. Do not change layers when routing from one DIMM to the next for multi-slot topologies. Additionally, it is recommended to route data byte groups on the highest signal layers (closest to the DIMM connector) as much as possible. Depending on the DIMM placement, the longest DQ bytes could be the center ones or the edge ones.
4. For fly-by routing, address, command, and control signals can be routed on different layers, but it is recommended to use as few as possible. Do not route any individual signal on more than two layers to minimize inductive loops that can lead to crosstalk issues. Any signal layer switching via needs to have one ground via within a 50 mil radius.
5. Versal device and memory drive strengths can vary based on the interface and topology. Refer to Answer Record 76059 for details.
6. If the system clock is connected to a bank that is also used for DDR4, LPDDR4, or LPDDR4x interfaces, the incoming clock signals must be biased so that they adhere to the signal level requirements of the I/O standard in the bank. Refer to the "AC Coupling Recommendations" section in Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) for specific requirements, as well as Answer Record 76062. The following figure shows the biasing structure from those reference documents for a DDR4 use case. AMD also recommends using DQS_BIAS with the unpopulated bias circuitry in place as a fallback option.
   Figure 1. AC-Coupled with DC-Biased Differential Clock Input
7. Signal lines must be routed over a solid reference plane. Avoid routing over voids, as shown in the following figure.
   Figure 2. Signal Routing Over Solid Reference Plane
   

   

   
   
8. Avoid routing over reference plane splits, as shown in the following figure.
   Figure 3. Signal Routing Over Reference Plane Split
   

   

   
   
9. Keep the routing at least 30 mils away from the reference plane and void edges with the exception of breakout regions, as shown in the following figure.
   Figure 4. Breakout Region Routing
   

   

   
   
10. Use chevron-style routing to allow for ground stitch vias. Figure 5 shows recommended routing for fly-by configurations, while Figure 6 shows recommended routing to accommodate ground stitch vias in a more congested clamshell configuration.
    Figure 5. Example of Ground Stitching (Fly-by)