The required signals used in DDR4 applications are shown in the following table. The signal list might vary slightly depending on the particular DDR4 architecture used.
Important: For dual-slot DIMM
topologies, place DIMM #0 on the furthest connector from the adaptive SoC to reduce
the effect of SI reflections. The DIMM #1 connector should be placed nearest to the
adaptive SoC.
| Signal | Description | Required PCB Termination 1 | Signal Routing Methodology |
|---|---|---|---|
| Clock Signals | |||
| CK_T/CK_C 2 | Address/Command Clock | See Figure 2 | Fly-by |
| Address Signals | |||
| A[17], A[13:0] | Address | 39Ω to VTT at far end | Fly-by |
| RAS_N/A[16] | Row Access Strobe | 39Ω to VTT at far end | Fly-by |
| CAS_N/A[15] | Column Access Strobe | 39Ω to VTT at far end | Fly-by |
| WE_N/A[14] | Write Enable | 39Ω to VTT at far end | Fly-by |
| BA[1:0] | Bank Address | 39Ω to VTT at far end | Fly-by |
| BG[1:0] | Bank Group | 39Ω to VTT at far end | Fly-by |
| Command/Control Signals | |||
| ACT_N | Activate Command | 39Ω to VTT at far end | Fly-by |
| CKE | Clock Enable | 39Ω to VTT at far end | Fly-by |
| CS_N | Chip Select | 39Ω to VTT at far end | Fly-by |
| ODT | On-Die Termination Enable | 39Ω to VTT at far end | Fly-by |
| PAR | Command/Address Parity | 39Ω to VTT at far end | Fly-by |
| Data Signals | |||
| DQ byte/nibble (8 or 4 bits each) |
Data | None, uses ODT | Point-to-point |
| DM/DBI (If present, one per byte) |
Data Mask/Data Bus Inversion | None, uses ODT | Point-to-point (4.7kΩ pull-up to VDDQ if unused) |
| Data Strobe Signals | |||
| DQS_T/DQS_C (one pair per byte/nibble) |
Data Strobe | None, uses ODT | Point-to-point |
| Miscellaneous Signals | |||
| RESET_N | Reset | 4.7 kΩ to GND at far end | Fly-by |
| DDR4 Devices/DIMMs Only | |||
| ALERT_N (devices) | CRC Error Flag Open-Drain Output | Connect ALERT_N pins as fly-by and terminate to VDD with a 50Ω resistor | Shared Pull-up |
| ALERT_N (DIMMs) | CRC Error Flag Open-Drain Output | None | None |
| TEN (devices) | Connectivity Test Mode Input | 500Ω to GND | One per memory device |
| ZQ (devices) | Calibration Reference | 240Ω to GND | One per memory device |
| EVENT_N (DIMM) | Temperature Event Open-Drain Output | Tie all EVENT_N pins in same interface to VDDSPD through 4.7 kΩ resistor | Shared Pull-up |
| Adaptive SoC Only | |||
|
IO_VR_7xx IO_VR_8xx (if present) |
Calibration Reference |
240Ω to VCCO_7xx 240Ω to VCCO_8xx (if present) |
|
|
|||
Important: For single-rank and
single-slot RDIMM configurations using the Optimum setting for Future Expansion for
PCB Design in the Vivado AXI NoC IP
customization tool, the DDR4 output clock pin sites are swapped in the nibble. The
CK_T pin is at an N site and the CK_C pin is at a P site. This is a known behavior
and does not have any functional impact during operation. Do not manually swap these
pins on the external memory interface because this causes the DDR4 clock to be out
of phase with the rest of the external signals.
Command/address/control (CAC) signals are routed in a fly-by pattern with far-end termination. DQ and DQS signals are routed point-to-point. The following figure shows examples of fly-by and point-to-point routing.
Figure 1. Point-to-Point (DQ/DQS) and Fly-by (CAC) Routing
Important: When
creating a DDR4 interface, all components in the interface must be the same (i.e.,
share the same part number, data width, density, and speed grade).
Figure 2. Far-End Termination for Differential Clock CK_T/CK_C
(Component Interfaces Only)
