PCB Noise

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English

PCB noise can arise due to coupling from one plane to another, either on the same layer or via adjacent layers.

Mitigating PCB Noise between VCCINT and VCC_RAM

Do not place sensitive rails close to noisy rails on the PCB. This can be accomplished best by a ground-power-ground layer arrangement. However, if using a ground-power-power-ground structure, ensure the distance between the power planes is large enough to reduce noise coupling, or do not place sensitive rails directly above/below noisy rails.

Add extra bypass capacitance on the PCB to lower the impedance of the rail. This requires simulations with the noise appropriately modeled. This is most effective for lower frequency noise, because high-frequency noise mitigation might require an excessive amount of appropriately-sized capacitors.

Separating VCCINT and VCC_RAM by a physical barrier, such as a ferrite bead or small conduit plane segment (see figure) can prevent high-frequency noise on one rail from reaching the other. However, this separation can also lead to an excessive IR drop across the bead/conduit which can hinder low-frequency bypass decoupling response. Extra bypass capacitors geared towards lower frequencies might be required close to the BGA balls of each respective rail.

Figure 1. VCCINT and VCC_RAM Combined