This section provides PCB design guidelines for LPDDR4/4x interfaces. Connections between the adaptive SoC and LPDDR4/4x device(s) are defined, along with physical design rules and timing constraints.
Note: To obtain maximum LPDDR4/4x speed, it is
recommended to keep the board thickness less than 131 mil. Trace length specifications
vary slightly based on board thickness. See Table 1 for trace length
rules.
Important: All routing
guidelines in this section must be followed to achieve the maximum data rates specified
in the Versal adaptive SoC
data sheets. Customers could have unique or specific designs with particular
violations of some rules. In these scenarios, design or routing trade-offs have to be
taken in other routing parameters to mitigate the risk. System-level channel signal
integrity simulations are required to evaluate such trade-offs. It is important to read
Required Memory Routing Guidelines for All Interfaces before continuing with this
section.