The timing constraints are defined in the following tables for various signal groups and their targets, similar to how they would be entered into PCB layout software tools. Adaptive SoC package delays should always be included for purposes of determining skews.
| Skew Constraint | Pin Pair Set | Minimum (ps) | Maximum (ps) | Group | Target |
|---|---|---|---|---|---|
| Address to Clock | Adaptive SoC to QDR-IV device | –6 | +6 |
A[21:0] AP AINV CFG_N LBK0_N LBK1_N LDA_N LDB_N RWA_N RWB_N |
CK_P |
| Data to DKA0 | Adaptive SoC to QDR-IV device | –5 | +5 | DQA[8:0] | DKA_P0 |
| Data to DKA1 | Adaptive SoC to QDR-IV device | –5 | +5 | DQA[17:9] | DKA_P1 |
| Data to DKB0 | Adaptive SoC to QDR-IV device | –5 | +5 | DQB[8:0] | DKB_P0 |
| Data to DKB1 | Adaptive SoC to QDR-IV device | –5 | +5 | DQB[17:9] | DKB_P1 |
| Data to QKA0 | Adaptive SoC to QDR-IV device | –5 | +5 |
DQA[8:0] QVLDA[0] |
QKA_P0 |
| Data to QKA1 | Adaptive SoC to QDR-IV device | –5 | +5 |
DQA[17:9] QVLDA[1] |
QKA_P1 |
| Data to QKB0 | Adaptive SoC to QDR-IV device | –5 | +5 |
DQB[8:0] QVLDB[0] |
QKB_P0 |
| Data to QKB1 | Adaptive SoC to QDR-IV device | –5 | +5 |
DQB[17:9] QVLDB[1] |
QKB_P1 |
| DK to CK | Adaptive SoC to QDR-IV device | 0 | +50 | DKA0_P DKA1_P DKB0_P DKB1_P |
CK_P |
| QK to CK | Adaptive SoC to QDR-IV device | 0 | +50 | QKA0_P QKA1_P QKB0_P QKB1_P |
CK_P |
| Clock 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
CK_P CK_N |
- |
| DKA0 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
DKA0_P DKA0_N |
– |
| DKA1 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
DKA1_P DKA1_N |
– |
| DKB0 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
DKB0_P DKB0_N |
– |
| DKB1 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
DKB1_P DKB1_N |
– |
| QKA0 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
QKA0_P QKA0_N |
– |
| QKA1 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
QKA1_P QKA1_N |
– |
| QKB0 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
QKB0_P QKB0_N |
– |
| QKB1 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
QKB1_P QKB1_N |
– |
|
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| Skew Constraint | Pin Pair Set | Minimum (ps) | Maximum (ps) | Group | Target |
|---|---|---|---|---|---|
| Address to Clock | Adaptive SoC to QDR-IV device | –6 | +6 |
A[20:0] AP AINV CFG_N LBK0_N LBK1_N LDA_N LDB_N RWA_N RWB_N |
CK_P |
| Data to DKA0 | Adaptive SoC to QDR-IV device | –5 | +5 | DQA[17:0] | DKA_P0 |
| Data to DKA1 | Adaptive SoC to QDR-IV device | –5 | +5 | DQA[35:18] | DKA_P1 |
| Data to DKB0 | Adaptive SoC to QDR-IV device | –5 | +5 | DQB[17:0] | DKB_P0 |
| Data to DKB1 | Adaptive SoC to QDR-IV device | –5 | +5 | DQB[35:18] | DKB_P1 |
| Data to QKA0 | Adaptive SoC to QDR-IV device | –5 | +5 |
DQA[17:0] QVLDA[0] |
QKA_P0 |
| Data to QKA1 | Adaptive SoC to QDR-IV device | –5 | +5 |
DQA[35:18] QVLDA[1] |
QKA_P1 |
| Data to QKB0 | Adaptive SoC to QDR-IV device | –5 | +5 |
DQB[17:0] QVLDB[0] |
QKB_P0 |
| Data to QKB1 | Adaptive SoC to QDR-IV device | –5 | +5 |
DQB[35:18] QVLDB[1] |
QKB_P1 |
| DK to CK | Adaptive SoC to QDR-IV device | 0 | +50 | DKA0_P DKA1_P DKB0_P DKB1_P |
CK_P |
| QK to CK | Adaptive SoC to QDR-IV device | 0 | +50 | QKA0_P QKA1_P QKB0_P QKB1_P |
CK_P |
| Clock 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
CK_P CK_N |
- |
| DKA0 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
DKA0_P DKA0_N |
– |
| DKA1 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
DKA1_P DKA1_N |
– |
| DKB0 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
DKB0_P DKB0_N |
– |
| DKB1 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
DKB1_P DKB1_N |
– |
| QKA0 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
QKA0_P QKA0_N |
– |
| QKA1 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
QKA1_P QKA1_N |
– |
| QKB0 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
QKB0_P QKB0_N |
– |
| QKB1 2 | Adaptive SoC to QDR-IV device | 0 | 2 |
QKB1_P QKB1_N |
– |
|
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