PCIe BARs Tab - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
Release Date
3.0 English

The PCIe BARs tab options for the AXI Bridge mode (Functional Mode option) is shown in the following figure.

Figure 1. PCIe BARs Tab for AXI Bridge Functional Mode

Base Address Register Overview

The Bridge core in Endpoint configuration supports up to six 32-bit BARs or three 64-bit BARs. The AXI Bridge for PCI Express® in Root Port configuration supports up to two 32-bit BARs or one 64-bit BAR.

BARs can be one of two sizes. BARs 0, 2, and 4 can be either 32-bit or 64-bit addressable. BARs 1, 3, and 5 can only be 32-bit addressable and are disabled if the previous BAR is enabled as 64-bit.

32-bit BARs
The address space can be as small as 4 kilobytes or as large as 2 gigabytes. Used for Memory to I/O.
64-bit BARs
The address space can be as small as 4 kilobytes or as large as 256 gigabytes. Used for Memory only.

All BAR registers share these options:

Click the checkbox to enable BAR. Deselect the checkbox to disable BAR.
BARs can be Memory apertures only. Memory BARs can be either 64-bit or 32-bit. Prefetch is enabled for 64-bit and not enabled for 32-bit. When a BAR is set as 64 bits, it uses the next BAR for the extended address space, making it inaccessible.
The available Size range depends on the PCIe Device/Port Type and the Type of BAR selected. The following table lists the available BAR size ranges
Table 1. BAR Size Ranges for Device Configuration
PCIe Device/Port Type BAR Type BAR Size Range
PCI Express Endpoint 32-bit Memory 4 Kilobytes - 2 Gigabytes
64-bit Memory 4 Kilobytes - 8 Exabytes
Identifies the ability of the memory space to be prefetched. This can only be enabled for 64-bit addressable bars.
The value assigned to BAR.
PCIe to AXI Translation
This text field should be set to the appropriate value to perform the translation from the PCI Express base address to the desired AXI Base Address.

Managing Base Address Register Settings

Memory indicates that the address space is defined as memory aperture. The base address register only responds to commands that access the specified address space. If MSI-X Capability Structure is enabled and MSI-X Internal implementation location is selected, there will be a 64 KB reserved address space in one of the enabled PCIe BAR. See the BAR Indicator option in the PCIe Misc Tab.

Disabling Unused Resources

For best results, disable unused base address registers to conserve system resources. A base address register is disabled by deselecting unused BARs in the AMD Vivado™ IDE.